World’s fastest IBM PCjr?

I added 128KB of memory inside of the FPGA and  disabled the MCL86 cycle compatibility with the original 4.77Mhz 8088 processor and got some interesting results:


If these speed test results are to be believed, then this IBM PCjr is many times faster than the original IBM PC XT and, for some tests, even faster than the 6Mhz IBM PC AT.



I am using DOS 2.1 and PCJRMEM.COM /C to allow these test programs to run from the upper/faster 128KB of memory.

It is interesting that Norton Utilities SI.EXE now thinks the processor is a NEC V20.  I think this may have something to do with the prefetch queue and the speed at which it fills when running programs from the upper/fast memory.

The lower 128KB physical DRAM is accessed in the normal fashion with four to six 4.77Mhz clock cycles.  The upper 128KB is located inside of the FPGA and is accessed in a number of 100Mhz clock cycles, so it is many times faster than the 4.77Mhz local bus.

The MCL86 clock cycle compatibility mode is turned off once the PCjr exits it’s POST. This means that once the microsequencer finishes processing an instruction it immediately fetches the next one. With cycle compatibility turned on, the microsequencer will pause for the same number of 4.77Mhz clock cycles that the original processor takes for that instruction.

Is this the world’s fastest IBM PCjr?  🙂

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World’s fastest IBM PCjr?

IBM PCjr running MCL86 with “Minimum Mode” BIU.

I just finished porting the MCL86 microsequencer-based 8088 core with a minimum-mode BIU (Bus Interface Unit) to a Xilinx Kintex-7 FPGA for use in an IBM PCjr!  Here are some videos of the PCjr in action:

IBM PCjr Music running on the MCL86 microsequencer based 8088 FPGA core

IBM PCjr Minuet running on the MCL86 microsequencer based 8088 FPGA core


The Xilinx Kintex-7 IOs are not 5V tolerant, so I added a Lattice ispMACH 4256ZE to translate between the Kintex and the PCjr’s motherboard.

The MCL86 core combined with the minimum-mode 8088 BIU consumes 1.5% of the Kintex-70T FPGA! Four block RAMS are used to hold the microcode.



It is interesting to note that when I disabled the cycle-accuracy of the MCL86 core, the PCjr would no longer pass it’s POST test. It would always beep twice and then enter a HALT state.  It appears that there is a test that depends on a particular completion time. Perhaps a timer test?

What I did to bypass this was to disable cycle-accuracy until the first NMI was received which should happen either at the end of the POST when the user makes the first key-press, or when the PCjr receives the keyboard “I am OK” information during it’s POST.

The PCjr runs noticeably faster when the cycle accuracy is disabled. The disk drive seek is faster and the warning bell when you try to use the keyboard when the CPU is busy is a higher pitch.

Here is the Norton Utility SI.EXE program running when cycle accuracy is enabled.



Below is a close-up of the FPGA setup. From the left there is a DIP-clip attached to the 8259 Interrupt Controller so I can probe the 8088 databus. Next to this is the 8088 adapter that is wired to the Lattice ispMACH 4256ZE breakout board which translates between the 5V motherboard and the 3.3V Xilinx Kintex FPGA. The Lattice board is wired to a board that contains the Kintex-7 FPGA.



My next project will be to integrate some of the PCjr’s memory into the FPGA which will be accessed at the processor’s core speed to see how much performance I can squeeze out of a PCjr!  The MCL86 core is a 16-bit processor and runs at 100Mhz, so theoretically should be able to access an on-FPGA RAM more than 10X faster than memory on the motherboard!

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IBM PCjr running MCL86 with “Minimum Mode” BIU.

Lockstep Quad Modular Redundant System

Just uploaded a few vidos to YouTube of an application that uses the MCL51, the microsequencer-based 8051 core.  It is a Lockstep Quad Modular Redundant System.

There are the links:

Lockstep QMR – Artix-7

Lockstep QMR – Spartan-6

The system consists of four modules that have independent voters and the ability to rebuild themselves using data broadcast from neighboring modules. The demonstration videos show modules rebuilding themselves and rejoining the lockstep after receiving multiple types of errors that are injected into each of them.

Because the modules use the microsequencer-based MCL51 processor, the footprint is very small. The complete system consumes around 12% of a Xilinx Artix-7 xc7a35 and about half of a xc6slx9 FPGA.


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Lockstep Quad Modular Redundant System

MCL86 running on Spartan-6

I recently picked up a Spartan-6 FPGA board from ebay (for $32!) so I thought it would be fun to load the MCL86 core and wire it up to an IBM PC 5150.  The Xilinx Spartan-6 LX9 costs close to $10 which is significantly cheaper than the $150+ Kintex-7.

Voltage dividers were used to translate between 5V and 3.3V and the FPGA’s IO drivers were set to PCI33 so the VCC clamp diodes would be enabled.  Around 10% of the FPGA’s logic was used by the MCL86 which implemented the 8088 Maximum Mode bus interface.

I read that back in the 80’s two software packages were used to judge if a computer was 100% IBM compatible. One was Lotus-123 and the other was Microsoft’s Flight Simulator. I have already run Lotus-123 successfully on the MCL86 but have not tried Flight Simulator until now.  I was not sure which version of the simulator was used, so I tried both!

Here it is:



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MCL86 running on Spartan-6

MCL51 Quad Core Demo

We just posted a video demonstration of a Quad Core MCL51 on YouTube:


Each core is running an independent application program.

Core-0: Parallel Port Blaster
Core-1: MIDI music player
Core-2: Sine wave generator using a R-2R DAC
Core-3: 115,200 UART Blaster

Four MCL51 8051 cores are instantiated along with a dual 24-bit timer and a UART.

A total of 1227 Artix-7 LUTs are consumed by this quad core processor which is less logic than most single core gate-based 8051 cores!


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MCL51 Quad Core Demo

MCL51 MIDI Player

We just uploaded a video to YouTube of the MCL51 playing “Flight of the Bumblebee” in MIDI format.  Here it is:


The program is entirely interrupt driven so the only “work” it does is either load a note into timer-0 or a delay into timer-1, after which controls passes back to the main loop. The music data takes about 2KB of Program ROM.

Below is the FPGA utilization using an Xilinx Atrix-7.  It is a little bigger than usual because we are translating the MIDI notes into thirty separate 24-bit counter registers.



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MCL51 MIDI Player

MCL51 fun with R-2R DAC

Having some fun with the MCL51 and an R-2R DAC.

We have two, eight-channel DACs made with a resistor ladder connected to the PMOD connectors of the Arty Xilinx Artix-7 test board.

The first picture uses the oscilloscope’s X-Y mode to display a 256×256 bit-mapped image.

The second and third images are made by sending the results of a lookup table to the PMOD connectors.

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MCL51 fun with R-2R DAC