TRS-80 Model I emulator uses MCLZ8 in a Teensy

I integrated the TRS-80 Model I ROMs into my MCLZ8 Z80 emulator and mapped the UART to the TRS-80’s keyboard and video RAM and now have it running on a standalone Teensy 4.1 board!

I am taking advantage of the high-speed USB UART to display the TRS-80 video RAM contents to the user. Whenever something is written to the video RAM, I simply output the complete 64×16 screen contents to the UART! It goes so fast that it looks like smooth motion – similar to flip-book animation.

In theory, it would be easy to map any memory or IO address to the Teensy’s GPIOs so one could write a BASIC program to control some pins on the board and could even implement a parallel bus… I am using the TRS-80 Model I ROMs at the moment. Probably no reason the Model III ROMs wouldn’t work just as well.

One other neat feature is that you can cut and paste a BASIC program into the UART window so you don’t need to type them in! 🙂

Source code is on GitHub: https://github.com/MicroCoreLabs/Projects/tree/master/MCLZ8/Code

TRS-80 Model I emulator uses MCLZ8 in a Teensy

MCLZ8 Videos – Games and Z80 Acceleration

I posted some videos to YouTube of a few games and also a small BASIC program to demonstrate the acceleration achieved when running the MCLZ8 is the maximum acceleration mode.

When using acceleration mode-3 which operates both RAM and ROM entirely inside of the Teensy and is accessed at 800Mhz, the total CPU speedup appears to be between 15x and 20x over the stock Z80! This is with “number crunching” only and not performing any video accesses which would slow down the CPU due to the video memory being located on the motherboard.

Video of Donkey Kong under NewDOS: https://www.youtubecom/watch?v=AHEyADtfJ3U

Video of Zaxxon under NewDOS: https://www.youtube.com/watch?v=NqiwF3rjT58

Video of Acceleration Demonstration under TRSDOS: https://www.youtube.com/watch?v=0iaphw76k6Q

I should have described the acceleration modes are in the videos, so ill correct that here:

Mode 0 – All external memory accesses
Mode 1 – Reads and writes are cycle accurate using internal memory with writes passing through to motherboard
Mode 2 – Reads accelerated using internal memory and writes are cycle accurate and pass through to motherboard
Mode 3 – All read and write accesses use accelerated internal memory

MCLZ8 Videos – Games and Z80 Acceleration

MCLZ8 – Testing Various Applications

My friend Ira Goldklang at http://www.trs-80.com sent me a number diskettes chock-full of applications to try on my MCLZ8 powered TRS-80 Model III. I’m happy to report that the testing was very successful! All of the DOS’s booted and allowed other diskette applications to be launched, all of the games that I tried seemed to fun fine, and some diagnostic programs reported happy results!

I plan to take a few videos soon, and one them will be of a diagnostic running with max acceleration which is rather amusing! So here are a few pictures of the progress so far and I will post more to this webpage as I try new applications and games

MCLZ8 – Testing Various Applications

MCLZ8 – Zilog Z80 Emulator in TRS-80 Model III

Update: Preliminary results indicate that the MCLZ8 is more than 15 times faster than the stock Z80 in the TRS-80 Model III. Stay tuned…

My latest project, the MCLZ8, is a Zilog Z80 emulator which can be used as a drop-in replacement for the original Z80. It uses a Teensy 4.1 microcontroller board which contains an 800Mhz microcontroller and a small PCB to perform the voltage translation between the motherboard and the microcontroller. The MCLZ8’s Z80 emulation passes the exhaustive ZEXALL opcode test suite and the speedy microcontroller allows the ability to simultaneously mimic the Z80’s local bus interface.

The MCLZ8 seems to work quite well as a Z80 replacement in a TRS-80 Model III where it runs BASIC and is able to boot from the diskette drive. I have tried NEWDOS and a number of games and I will test more applications in the near future.

Of course the next step will be to see how much acceleration we can achieve! 🙂 If we eliminate cycle-accuracy, locate the RAM and ROM into the MCLZ8’s internal RAM and access them at the top speed of the microcontroller we should get some very interesting results! There have been a number of TRS-80 accelerators over its history, so it will be interesting to see where the MCLZ8 ranks!

But for now I am happy to see the MCLZ8 working inside of this legendary computer!

MCLZ8 – Zilog Z80 Emulator in TRS-80 Model III

Zilog Z80 Emulator – MCLZ8

I am beginning work on a Zilog Z80 emulator which runs on an Teensy 4.1 that can be used as a drop-in replacement for the original Z80. I recently bought a TRS-80 Model III to test this with…

The first step is to figure out which Z80 IO’s will map to the Teensy 4.1 and also any buffers that are needed to translate between 3.3V and 5V. I found that four buffers will do the trick with one of them being used to latch the lower eight Z80 address signals.

Many of the IOs will be the same as the MCL86+ which is my 8088 emulator, which will save a lot of time!

The board is now being built, so I have time to write the actual Z80 emulator code. I will start with the bus interface and then expand to support the multiple levels of opcode decode and then the actual opcodes themselves!

Zilog Z80 Emulator – MCLZ8

MCL86+ Design Notes and Challenges

There were a number of challenges which needed to be overcome to be able to emulate the Intel 8088 correctly, be cycle accurate, and allow the MCL86+ to actually replace the Intel CPU in an IBM PC.

The initial concept was to see if it was possible to use the speed of an 800Mhz microcontroller to both emulate the 8086 instruction set and also manage the 8088’s local bus interface which is running at 4.77Mhz. I had recently finished the MCL65+ which is similar 6502 emulator, however this CPU only runs at 1Mhz – so 4.77Mhz was going to be more challenging, if possible at all…

I wrote some code which performed basic reads and writes on the local bus and was not surprised to find that it did not make timing. I tried direct accesses to the Teensy’s GPIOx registers to allow for a faster and more parallel accesses to the IO pins which still wasn’t fast enough due to the bit shifting and isolating to steer the 8088 address and data signals to the correct Teensy GPIOs. I found that using a few arrays to perform this mapping reduced this translation time significantly. For additional margin I am also running the Teensy 4.1 overclocked at 800Mhz which, according to the GUI, does not need cooling and I have found that it runs reliably at this speed. I also noticed that occasionally 8088 clocks were being lost, so I disabled Teensy interrupts while an 8088 bus cycle is in progress. After this code was running reliably I could then begin development of the MCL86+ PCB.

I used KiCad to generate the schematics and PCB layout. I tried to select Teensy IOs which closely routed to the appropriate 8088 pin and also to maximize the Teensy’s GPIOx register utilization. Because the target of this project was to run on the IBM PC I only needed to support the 8088’s Maximum mode which meant I would only need three 8-bit buffers on the MCL86+ to perform voltage translation. The Teensy 4.1 had enough pins to allow me to separate the databus inputs and output pins which would yield faster bus timing since I would not need to program the Teensy IO/s to change direction between input and outputs.

While the PCB was being built I had time to write the code for the 8086 emulator. A few years ago I wrote an x86 emulator for my MCL86 project which is a microsequencer-based FPGA core which also runs cycle accurate and accelerated modes, so I was already familiar with the 8088’s instruction set and also the “structural” aspects of the processor such as the ordering of interrupts, the operation of the prefix opcodes, and the prefetch queue.

The 8088 emulator code, like the real 8088, is divided into two sections: The Bus Interface (BIU) and the Execution Unit (EU). This allowed me to either use a BIU which accesses the real 8088 pins, or instead use a “fake” BUI which uses arrays for RAM and ROM so I cold develop and test the emulator using command-line C and printf’s. I wrote a number of opcodes tests fort the 8086 when I developed the MCL86, which saved a lot of time debugging the MCL86+.

Of course the MCL86+ did not immediately work when I first plugged it into the IBM PC; however it did fetch instructions and produce some results to the CGA display when I ran the SuperSoft Diagnostic ROM. Some of the initial bugs were that I was not latching all of the 8088 address lines for the duration of the bus cycle. I also was pushing the wrong address to the stack for a CALL opcode, and the final bug was that I was not flushing the prefech queue upon one of the CALL opcodes. After that it was able to run just about any program I tried on it!

The next fun part was to try some acceleration! The first and easing thing to do was to simply disable the clock counter which allows the emulator to be cycle accurate. This yielded a nearly 50% improvement in speed as reported by a few benchmark programs. It was also not such a great degree of acceleration that things like the disk drive, keyboard, and timers seemed to still work.

I then tried integrating some of the motherboard’s RAM and ROMS and running them at the speed of the 800Mhz Teensy 4.1’s microcontroller but got very interesting, yet disappointing results…

When running the SuperSoft Diagnostic ROM the computer ran significantly faster than stock! Perhaps close to 10 times faster… But when I booted to BASIC, it will not able to accept keystrokes from the keyboard,. The speed was also too fast to boot from the disk drive; so I was not able to run any benchmarks to see what the acceleration yielded. One problem is that the IBM disk drives use DMA to copy data to/from the motherboard RAM, but if I emulated this RAM inside of the MCL86+ is it no longer coherent with that on the the motherboard, Perhaps if I had an XT-IDE which does not use DMA I could make further progress.

But, for now the design goals were met and it is time to move on to the next project.

All of the project files, the emulator source, the schematics, and the PCB fabrication files are on GitHub.

MCL86+ Design Notes and Challenges

MCL86+ 8088 Accelerator – Results

To see what kind of acceleration is possible on the MCL86+ I located the SuperSoft Diagnostic ROM and 256KB of RAM inside of the Teensy 4.1 micro controller so they will be accessed at closer to 800Mhz instead of the bus cycle-accurate 4.77Mhz. I also disabled cycle accuracy so that 8088 opcodes will also run at the speed of the microcontroller!

I took a short video and posted it on YouTube: https://youtu.be/xXVImaMU7Hw

There is quite a bit of acceleration … Quite a few times faster than the 4.77Mhz 8088. The entire SuperSoft Diagnostics test runs in about 35 seconds!

Unfortunately, I can’t run much of anything else! It appears that Microsoft BASIC cannot handle this amount of acceleration. It boots to BASIC, however it will not accept keystrokes. I cannot boot anything from the disk drive either at this speed, and if I first boot from the disk and then enable acceleration, the data is not coherent between the motherboard’s memory and the memory in the MCL86+ due to the disk drive DMA. I may need something like an XT-IDE which doesn’t use DMA to guarantee that all memories are coherent.

There are probably a number of software solutions which could address this. Perhaps being sensitive to certain interrupts and slowing down to cycle-accurate mode while they run would solve the BASIC and disk drive speed problems. Maintaining coherence between the internal and motherboard RAM could also potentially be solved by simply performing a “sync” after a disk access has occurred where the MCL86+ would just copy the RAM contents from the motherboard to the internal RAM, and then continue the program.

Oh well. Making an 8088 accelerator was not the design goal of this project. The challenge was to see if I could implement a 8088 software emulation running on a fast microcontroller and also support its bus interface while maintaining close to cycle accuracy. It is a more complicated project than the MCL65+ which emulates a 6502 and also supports the bus interface which was somewhat easier as the 6502 has a simpler instruction set, and the bus interface only runs at 1Mhz. The MCL86+ was quite a bit more challenging! It only took a few months to achieve the goal… so Yay! 🙂

The schematics, PCB, and C code are on GitHub: https://github.com/MicroCoreLabs/Projects/tree/master/MCL86%2B

MCL86+ 8088 Accelerator – Results

MCL86+ Running a few benchmarks

I tweaked the clock cycle counter a little to try to get a little closer to the speed of the genuine 8088, but different benchmarks yield different results! It is possible to dial in each of the hundreds of 8088 opcodes, but I will leave that as a project for another day.

Below are a few benchmark tests, plus the 8088 MPH demo which some consider a benchmark application.

Here is the results from the DOS program MIPS.COM

Here is the Norton Utilities System Information:

Here is a screenshot of the 8088 MPH Demo. I only have 256KB of RAM on this motherboard so I believe the software skips some demos which require the full 640KB of RAM.

Here is the YouTube video of the MCL86+ running the demo: https://youtu.be/AAgtQljp0Tc

MCL86+ Running a few benchmarks