MCL86jr on the way

I just finished the layout for the MCL86jr, which is a small board which can replace the 8088 CPU in the IBM PCjr. It uses my MCL86 CPU core with a “minimum” mode BIU (Bus Interface Unit) and is implemented in a Xilinx Spartan-6 FPGA. The board contains a 512KB Static RAM which can bring the PCjr’s total RAM to 640KB or can be used to mirror and accelerate the BIOS ROM or even load PCJr cartridge images!

The MCL86 core can be used in “cycle accurate” mode to the original 4.77Mhz clock speed, or it can be unlocked to run significantly faster. I used this mode a few years ago to create the world’s fastest PCjr! https://microcorelabs.wordpress.com/2017/01/02/worlds-fastest-pcjr/

Project under MCL86 in GitHub: https://github.com/MicroCoreLabs/Projects

MCL86jr on the way

Brother Word Processor Arduino Project

Small project which allows user to control the Brother Word Processor as a remote keyboard using an Arduino.  You can paste a block of text into the terminal which will be sent to the typewriter for quick printing!

Here is a video of it in action:   YouTube video link

And here is the source code on GitHub:  GitHub link

This was a small weekend project to have some fun with a vintage typewriter/word processor. The serial interface to the word processor is a simple two-wire interface of clock and data where characters are sent as 8-bits.  The longest part of the project was using the logic analyzer to examine what the encoding was for each character!

20200828_212104

Brother Word Processor Arduino Project

LED Array Articles

I recently helped my friend Clive “Max” Maxfield with his 12×12 ping-pong LED array by making a simulator which runs on the Arduino GUI so that anyone can create and test a program to run on Max’s LED array.

The idea is that people can develop their own application and test it using my simulator, then submit it to Max so he can run it on the real 12×12 LED array. He will then post a video of the submission!

Here are the articles:

LED Simulator Article Part I

LED Simulator Article Part II

 

 

LED Array Articles

RISC-V Emulator written in C

I uploaded to GitHub a RISC-V CPU emulator for the RV32I instruction set written in C. It was a fun little project which did not take very long and gave me a chance to get more familiar with this instruction set.

There are a few RISC-V software versions out there, but my hope was to write something very simple and accessible. It only has 130 lines of code including comments!

Each loop though main() is effectively a single RISC-V clock tick.  So one instruction per tick/loop.  At the end of each loop I print out the program counter, the instruction’s name, some registers and decoded opcode parameters, then it waits for a keypress.  This way you can single-step through your code and see the internals of the CPU!

Have fun!

-Ted

Here’s the link to the code:   RISC-V C Version

 

Example Single-stepping through some RV32I code:

PC:0x0 Opcode:0x403150b3  SRA rd:1 rs1:2 rs2:3    U_immediate:0x40315    J_immediate:0x15c02    B_immediate:0xc00    I_immediate:0x403    S_immediate:0x401    funct3:0x5   funct7:0x20

Regs: r0:0 r1:800 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x4 Opcode:0x3120b3  SLT rd:1 rs1:2 rs2:3    U_immediate:0x312    J_immediate:0x12802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x2   funct7:0x0

Regs: r0:0 r1:0 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x8 Opcode:0x3100b3  ADD rd:1 rs1:2 rs2:3    U_immediate:0x310    J_immediate:0x10802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x0   funct7:0x0

Regs: r0:0 r1:1001 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0xc Opcode:0x40315093  SRAI rd:1 rs1:2 rs2:3    U_immediate:0x40315    J_immediate:0x15c02    B_immediate:0xc00    I_immediate:0x403    S_immediate:0x401    funct3:0x5   funct7:0x20

Regs: r0:0 r1:200 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x10 Opcode:0x315093  SRLI rd:1 rs1:2 rs2:3    U_immediate:0x315    J_immediate:0x15802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x5   funct7:0x0

Regs: r0:0 r1:200 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x14 Opcode:0x311093  SLLI rd:1 rs1:2 rs2:3    U_immediate:0x311    J_immediate:0x11802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x1   funct7:0x0

Regs: r0:0 r1:8000 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

RISC-V Emulator written in C

Lockstep Quad Modular Redundant System uploaded to Github

I just uploaded my Lockstep Quad Modular Redundant System to Github! The system contains four MCL51’s which are tiny microsequencer-based 8051 compatible CPUs that are running in lockstep. My feeling was that TMR (Three Module Redundancy) is good, but what if one of the modules fails? Then you would have a vulnerable system with only two healthy modules. My solution was to add a CPU bringing the count to four CPUs running in lockstep! The best part of the system is that if a module fails, it can rebuild itself and then rejoin the lockstep! This is possible because of the microsequencer-based implementation of the processor. I believe this makes this system unique as most n-modular redundant systems do not have the ability to heal themselves and rejoin the lockstep! 🙂

Here is the Github link:  GitHub Lockstep QMR

And here are a few articles written about it a while ago:

EE Times

Xilinx Daily Blog

Enjoy! -Ted

Lockstep Quad Modular Redundant System uploaded to Github