MCL51 Utilization using Xilinx Kintex

Utilization of the MCL51 Execution Unit which contains the microsequencer and the associated registers and logic which are a bulk of the MCL51 core. This does not include the SFR registers, peripherals, or code and data memories.

Xilinx Kintex  XC7K70T :       194 LUTS and one RAMB

 

MCL51_Kintex

Please visit us at: www.MicroCoreLabs.com for more information.

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MCL51 Utilization using Xilinx Kintex

MCL51 Testing Method

The MicroCore Labs MCL51 was tested in three stages:

During the first stage, an exhaustive set of tests was written in assembly code which would exercise each 8051 opcode and then observe the results. PSW flags were checked whether or not the instruction generated a change in their status and all four register banks were cleared and rechecked to guarantee that the opcode did not affect registers or memory outside of the intended destination. Each boolean instruction was run on multiple memory ranges that support bit-mapped operations while mathematic and string  instruction were run against all possible data values.

After these tests were developed they were run against multiple simulation tools, some of them major vendors. I was interested to find that some of the tools were not 100% correct for every 8051 instruction!  Who the vendors are and what are the errors? I’m not telling. 🙂

Once the tests were validated against multiple vendor simulators I then wired up a system to run the tests on real silicon. I chose a ROM-less 8051 variant that came in a 40-pin package and had 3.3V IOs.  This allowed be to connect it directly to an FPGA test board which you see below:

 

IMG_3364

The test code uses simple loops when it reaches a failure, so it was easy to run the test and simply look at the scope to see if it was running in any infinite loops. When it looped to a final address it showed that all of the tests had run successfully. The test code is nearly 6KB so it was divided into three sections and tested independantly.

After the test code was validated by known correct simulators and real silicon I was then ready to run it against the MCL51 core in my Verilog simulation environment. I am pleased that while a few subtle bugs were corrected in the MCL51 core using this test suite, I am now very confident that the core is 100% compatible and correctly implements the 8051 instruction set!

Please visit us at: www.MicroCoreLabs.com for more information.

MCL51 Testing Method

Alpha MCL51 now available

 

The MicroCore Labs MCL51 is now available for  Alpha users!

The MCL51 is an ultra-small footprint, microsequencer-based, 8051 instruction-set compatible, embedded processor core that can be implemented in any FPGA or ASIC technology.

 

Key Features:

  • 100% Compatible with 8051 instruction set
  • Vectored interrupts with up to 128 sources
  • Proxy addressing for peripherals to allow any bus size
  • Bus Interface Unit allows high degree of peripheral customization

 

The MCL51 is an embedded processor core implemented with a high performance 32-bit microsequencer which utilizes less than 200 Xilinx LUTS and a single block RAM. It is 100% compatible with the classic 8051 instruction set and has a Bus Interface Unit (BIU) that provides the maximum degree of flexibility to implemented SFR registers and peripherals customized to the user’s design. Improvements to the original 8051 include up to 128 vectored interrupts as well as a proxy addressing system which allows the user to connect peripherals of any bus width to the core.

The core was run against a rigorous suite of tests which were validated using a major simulation tool as well as on genuine 8051 hardware.

 

Please visit us at: www.MicroCoreLabs.com for more information.

Alpha MCL51 now available