World’s fastest IBM PCjr

I added 128KB of memory inside of the FPGA and  disabled the MCL86 cycle compatibility with the original 4.77Mhz 8088 processor and got some interesting results:


If these speed test results are to be believed, then this IBM PCjr is many times faster than the original IBM PC XT and, for some tests, even faster than the 6Mhz IBM PC AT.



I am using DOS 2.1 and PCJRMEM.COM /C to allow these test programs to run from the upper/faster 128KB of memory.

It is interesting that Norton Utilities SI.EXE now thinks the processor is a NEC V20.  I think this may have something to do with the prefetch queue and the speed at which it fills when running programs from the upper/fast memory.

The lower 128KB physical DRAM is accessed in the normal fashion with four to six 4.77Mhz clock cycles.  The upper 128KB is located inside of the FPGA and is accessed in a number of 100Mhz clock cycles, so it is many times faster than the 4.77Mhz local bus.

The MCL86 clock cycle compatibility mode is turned off once the PCjr exits it’s POST. This means that once the microsequencer finishes processing an instruction it immediately fetches the next one. With cycle compatibility turned on, the microsequencer will pause for the same number of 4.77Mhz clock cycles that the original processor takes for that instruction.

Is this the world’s fastest IBM PCjr?  🙂

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World’s fastest IBM PCjr

IBM PCjr running MCL86 with “Minimum Mode” BIU.

I just finished porting the MCL86 microsequencer-based 8088 core with a minimum-mode BIU (Bus Interface Unit) to a Xilinx Kintex-7 FPGA for use in an IBM PCjr!  Here are some videos of the PCjr in action:

IBM PCjr Music running on the MCL86 microsequencer based 8088 FPGA core

IBM PCjr Minuet running on the MCL86 microsequencer based 8088 FPGA core


The Xilinx Kintex-7 IOs are not 5V tolerant, so I added a Lattice ispMACH 4256ZE to translate between the Kintex and the PCjr’s motherboard.

The MCL86 core combined with the minimum-mode 8088 BIU consumes 1.5% of the Kintex-70T FPGA! Four block RAMS are used to hold the microcode.



It is interesting to note that when I disabled the cycle-accuracy of the MCL86 core, the PCjr would no longer pass it’s POST test. It would always beep twice and then enter a HALT state.  It appears that there is a test that depends on a particular completion time. Perhaps a timer test?

What I did to bypass this was to disable cycle-accuracy until the first NMI was received which should happen either at the end of the POST when the user makes the first key-press, or when the PCjr receives the keyboard “I am OK” information during it’s POST.

The PCjr runs noticeably faster when the cycle accuracy is disabled. The disk drive seek is faster and the warning bell when you try to use the keyboard when the CPU is busy is a higher pitch.

Here is the Norton Utility SI.EXE program running when cycle accuracy is enabled.



Below is a close-up of the FPGA setup. From the left there is a DIP-clip attached to the 8259 Interrupt Controller so I can probe the 8088 databus. Next to this is the 8088 adapter that is wired to the Lattice ispMACH 4256ZE breakout board which translates between the 5V motherboard and the 3.3V Xilinx Kintex FPGA. The Lattice board is wired to a board that contains the Kintex-7 FPGA.



My next project will be to integrate some of the PCjr’s memory into the FPGA which will be accessed at the processor’s core speed to see how much performance I can squeeze out of a PCjr!  The MCL86 core is a 16-bit processor and runs at 100Mhz, so theoretically should be able to access an on-FPGA RAM more than 10X faster than memory on the motherboard!

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IBM PCjr running MCL86 with “Minimum Mode” BIU.