RISC-V Emulator written in C

I uploaded to GitHub a RISC-V CPU emulator for the RV32I instruction set written in C. It was a fun little project which did not take very long and gave me a chance to get more familiar with this instruction set.

There are a few RISC-V software versions out there, but my hope was to write something very simple and accessible. It only has 130 lines of code including comments!

Each loop though main() is effectively a single RISC-V clock tick.  So one instruction per tick/loop.  At the end of each loop I print out the program counter, the instruction’s name, some registers and decoded opcode parameters, then it waits for a keypress.  This way you can single-step through your code and see the internals of the CPU!

Have fun!

-Ted

Here’s the link to the code:   RISC-V C Version

 

Example Single-stepping through some RV32I code:

PC:0x0 Opcode:0x403150b3  SRA rd:1 rs1:2 rs2:3    U_immediate:0x40315    J_immediate:0x15c02    B_immediate:0xc00    I_immediate:0x403    S_immediate:0x401    funct3:0x5   funct7:0x20

Regs: r0:0 r1:800 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x4 Opcode:0x3120b3  SLT rd:1 rs1:2 rs2:3    U_immediate:0x312    J_immediate:0x12802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x2   funct7:0x0

Regs: r0:0 r1:0 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x8 Opcode:0x3100b3  ADD rd:1 rs1:2 rs2:3    U_immediate:0x310    J_immediate:0x10802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x0   funct7:0x0

Regs: r0:0 r1:1001 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0xc Opcode:0x40315093  SRAI rd:1 rs1:2 rs2:3    U_immediate:0x40315    J_immediate:0x15c02    B_immediate:0xc00    I_immediate:0x403    S_immediate:0x401    funct3:0x5   funct7:0x20

Regs: r0:0 r1:200 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x10 Opcode:0x315093  SRLI rd:1 rs1:2 rs2:3    U_immediate:0x315    J_immediate:0x15802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x5   funct7:0x0

Regs: r0:0 r1:200 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

PC:0x14 Opcode:0x311093  SLLI rd:1 rs1:2 rs2:3    U_immediate:0x311    J_immediate:0x11802    B_immediate:0x800    I_immediate:0x3    S_immediate:0x1    funct3:0x1   funct7:0x0

Regs: r0:0 r1:8000 r2:1000 r3:1 r4:4 r5:0 r6:0 r7:0 r8:0 r9:0 r10:0 r11:0 r12:0 r13:0 r14:0 r15:0 r16:0 r17:0 r18:0 r19:0 r20:0 r21:0 r22:0 r23:0 r24:0 r25:0 r26:0 r27:0 r28:0 r29:0 r30:0 r31:0

Memory: Addr0:0 Addr1:0 Addr2:0 Addr3:0 Addr4:0 Addr5:0 Addr6:0

RISC-V Emulator written in C

Lockstep Quad Modular Redundant System uploaded to Github

I just uploaded my Lockstep Quad Modular Redundant System to Github! The system contains four MCL51’s which are tiny microsequencer-based 8051 compatible CPUs that are running in lockstep. My feeling was that TMR (Three Module Redundancy) is good, but what if one of the modules fails? Then you would have a vulnerable system with only two healthy modules. My solution was to add a CPU bringing the count to four CPUs running in lockstep! The best part of the system is that if a module fails, it can rebuild itself and then rejoin the lockstep! This is possible because of the microsequencer-based implementation of the processor. I believe this makes this system unique as most n-modular redundant systems do not have the ability to heal themselves and rejoin the lockstep! 🙂

Here is the Github link:  GitHub Lockstep QMR

And here are a few articles written about it a while ago:

EE Times

Xilinx Daily Blog

Enjoy! -Ted

Lockstep Quad Modular Redundant System uploaded to Github

Arduino-based Wheelwriter Printer

Hi,

I just uploaded a small project to GitHub which is an Arduino implementation of a “Printer Option” for some of the IBM Wheelwriter typewriters.  It allows the user to connect to this typewriter via a RS232 serial port. You can cut and paste into the terminal window (300 baud) to allow using the typewriter as a printer!

This is my first Arduino project which was a lot of fun!

Here’s the GitHub project:   GitHub Wheelwriter Project

And a video of it in action.. well, slow action… YouTube Video

Enjoy!

-Ted

20191109_205529

 

 

20191109_20344720191109_203425.jpg

 

20191109_203436.jpg

Arduino-based Wheelwriter Printer

IBM Wheelwriter Printer Option

Hi,

I just uploaded a small project to GitHub which is an FPGA implementation of a “Printer Option” for some of the IBM Wheelwriter typewriters.  It allows the user to connect to this typewriter via a RS232 serial port. You can cut and paste into the terminal window (9600 baud) to allow using the typewriter as a printer!

Here’s the link:   Wheelwriter Printer Option

And here’s a short video demonstration:  FPGA Demo of Wheelwriter Printer Option

 

Enjoy!

-Ted

 

20191103_121814
MicroCore Labs – IBM Wheelwriter Printer Option
—————————————————————————————-
Description:
————
This is an FPGA project which allows RS232 access to an IBM Wheelwriter Typewriter.

Using a terminal running at 9600 baud (9600,n,8,1), the user can directly send characters to the typewriter.  They can also cut and paste long documents into the terminal, which will be printed by the typewriter. The FPGA uses XON/XOFF for flow control as well as a 1,000 character deep FIFO so that no characters are lost.

It has been tested on an IBM Wheelwriter 5, however other IBM typewriters such as the Wheelwriter 3 and 6 may also work. The only connection needed to the typewriter is via two pins within the access panel at the top rear of the typewriter.

While any FPGA can be used, this project uses the Lattice XO2 Breakout Board which contains a USB interface that provides  power and a RS232 serial port. To use the USB serial port, the user will need to populate the two resistors R14 and R15 which connect the RS232 TX and RX lines between the FPGA and the FTDI USB IC.

Alternatively, a second set of RS232 TX and RX pins are available which can be connected to any 3.3V compatible serial port. This was provided to allow to user to connect any type of serial port, including vintage computers. Just make sure the TTL signalling out of the converter is 3.3V to the FPGA. Both serial connections can be connected at the same time, however only one can be used at a time. In both cases, the baud rate is fixed to 9600 baud only.

20191103_121807

Architecture:
————————
1) RS232 RX controller – fixed to 9600 baud
2) RX character FIFO – 1,000 characters deep – flags used to signal RS232 transmit of XON/XOFF
3) RS232 TX controller – fixed to 9600 baud – Used to send XON/XOFF flow control characters
4) Main Controller – Pulls new characters from the RX_FIFO and sends the appropriate command sequence to the IBM TX_FIFO
5) IBM Bus Controller – Pulls commands from the FIFO and sends them serially over the IBM_BUS
6) Bus Snooper – Used to convert IBM serial data into parallel data to be observed on a logic analyzer. Not used for the design, just for debug

20191103_121824
Notes:
———-
– The IBM_BUS uses 5 volt logic, so a 5V to 3.3V bidirectional level shifter must be used. I used a Xilinx EPLD board,
but any technology will work that provideds this functionality.
– Both serial ports on the FPGA have light internal pullups to keep them from changing when not connected.

20191103_12183420191103_121840
Pinout
——-
– The pinout for the FPGA is described in the mclwr1.lpf file
– The IBM Wheelwriter pins of interest are: 4=GND and 5=IBM_BUS. Pin#1 is on the left when looking at the typewriter from the front.

 

IBM Wheelwriter Printer Option

MCLR5 QUAD-ISSUE SUPERSCALAR RISC V

I have completed the framework for the MCLR5 Quad-issue Supersclar RISC v core. It supports most of the RV32I Base Instruction Set with exceptions for the timers and shifters. I have targeted the core to the Xilinx Ultrascale+ and the Intel Stratix-10 series FPGAs.

Each of the MCLR5 RISC V cores is implemented as a combinational, single-cycle ALU.  Up to four register updates can occur per clock cycle and results are are forwarded to the appropriate cores when appropriate within the same clock cycle.  This just means that if core0 updates r4 and core1 uses r4 as an input, the updated value will be passed to core1.

Loads and stores are handled by core0 and are treated initially as JUMP opcodes. The MCLR5 performs a JUMP to the address containing the LOAD/STORE instruction which aligns it with core0. Instructions following the LOAD/STORE are blocked until the LOAD/STORE is completed.

The User’s Program ROM is four-opcodes wide and dual-ported so any instruction alignment is supported. Only one clock is consumed for JUMP opcodes. Because the ALU is single-cycle, no other pipelining penalties are incurred.

The Quad-issue Superscalar MCLR5 achieves nearly 90Mhz when targeted to Stratix-10 or Ultrascale+.  A Single MCLR5 can reach over 250Mhz.  The relatively slow timing of the quad-issue core is due to the very long combinaional paths through all four cores which is not surprising.  I am actually impressed that these clock frequencies were reached at all.  🙂

It is hard to come up with a picture to illustrate a quad-issue CPU core, so I will just post a screen-shot of a sixteen ADD r1 , r1 , 1  instructions with a SW stuck in the middle.

Capture

 

 

 

MCLR5 QUAD-ISSUE SUPERSCALAR RISC V