Received the Apple II+ in the mail today but it did not come with any diskettes. I used a terrific tool, ADTPro, to transfer disk images from my PC over to the Apple using the cassette port. It is slow but works great! I was able to transfer over DOS 3.3 and a few games such as Castle Wolfenstein, Zaxxon, and Lode Runner. They all appear to work fine with the MCL65 and I will take some pictures and video in a day or so.
Just ported the MCL65 to a Xilinx Spartan-3 board which contains an XC3S250E.
490 LUTs are used, which is 10% of the device.
Here are a few pictures of the MCL65 running on a VIC20.
Video is available at MicroCore Labs YouTube Channel
The MCL65 is currently running inside of a Commodore VIC-20 computer! I have no game cartridges at the moment, so I am just running the classic a=a+1 BASIC counting program.
I am using a Digilent Arty S7 board which has a Xilinx Spartan-7 XC7S50. The core utilizes about 0.77% of the device!
The MCL65 is designed to be cycle-exact to the original MOS 6502 microprocessor, so it should be able to run timing-dependent computers like the Apple II’s. ( I believe the disk controller requires certain instruction cycle timing). Hopefully I can get one of these machines soon to give it a try.
I also hope to test the core on an Atari-2600, and a Commodore-64.
Pictures and videos will be coming soon!
I added 128KB of memory inside of the FPGA and disabled the MCL86 cycle compatibility with the original 4.77Mhz 8088 processor and got some interesting results:
If these speed test results are to be believed, then this IBM PCjr is many times faster than the original IBM PC XT and, for some tests, even faster than the 6Mhz IBM PC AT.
I am using DOS 2.1 and PCJRMEM.COM /C to allow these test programs to run from the upper/faster 128KB of memory.
It is interesting that Norton Utilities SI.EXE now thinks the processor is a NEC V20. I think this may have something to do with the prefetch queue and the speed at which it fills when running programs from the upper/fast memory.
The lower 128KB physical DRAM is accessed in the normal fashion with four to six 4.77Mhz clock cycles. The upper 128KB is located inside of the FPGA and is accessed in a number of 100Mhz clock cycles, so it is many times faster than the 4.77Mhz local bus.
The MCL86 clock cycle compatibility mode is turned off once the PCjr exits it’s POST. This means that once the microsequencer finishes processing an instruction it immediately fetches the next one. With cycle compatibility turned on, the microsequencer will pause for the same number of 4.77Mhz clock cycles that the original processor takes for that instruction.
Is this the world’s fastest IBM PCjr? 🙂
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