Im working on a Quad-issue Superscalar RISC V processor at the moment and I thought I would share an exciting milestone….
This is a simulation snippet of four RISC V ADDI r1,r1,0x1 instructions in a row. The core fetches and executes the four instructions simultaneously and writes it back to r1, all in one clock cycle. Neat!!!
The MCLR5 is a quad-issue superscalar RISC V processor core with single-cycle instruction timing. There are four combinational RISC V ALU cores which process four consecutive instructions and can update up to four registers per clock cycle. The core should come fairly close to an aggregate IPC of nearly four.
For those who are interested: MCL65
Received the Apple II+ in the mail today but it did not come with any diskettes. I used a terrific tool, ADTPro, to transfer disk images from my PC over to the Apple using the cassette port. It is slow but works great! I was able to transfer over DOS 3.3 and a few games such as Castle Wolfenstein, Zaxxon, and Lode Runner. They all appear to work fine with the MCL65 and I will take some pictures and video in a day or so.
Just ported the MCL65 to a Xilinx Spartan-3 board which contains an XC3S250E.
490 LUTs are used, which is 10% of the device.
Here are a few pictures of the MCL65 running on a VIC20.
Video is available at MicroCore Labs YouTube Channel