Im working on a Quad-issue Superscalar RISC V processor at the moment and I thought I would share an exciting milestone….
This is a simulation snippet of four RISC V ADDI r1,r1,0x1 instructions in a row. The core fetches and executes the four instructions simultaneously and writes it back to r1, all in one clock cycle. Neat!!!
The MCLR5 is a quad-issue superscalar RISC V processor core with single-cycle instruction timing. There are four combinational RISC V ALU cores which process four consecutive instructions and can update up to four registers per clock cycle. The core should come fairly close to an aggregate IPC of nearly four.