Well at least *one* of the the world’s fastest Commodore 64’s 🙂
There are also the SuperCPU and Chameleon FPGA platforms which are either extremely expensive or unobtainable. The MCL64 board coupled with the Teensy 4.1 cost less than $50!
When I locate most of the C64’s memory ranges inside of the micro controller and disable cycle accurate mode (1Mhz native mode) the 6510 is emulated at over 600Mhz on a dual-issue superscalar processor, so it’s no surprise that we can achieve such a speed improvement!
The project is now on GitHub: https://github.com/MicroCoreLabs/Projects/tree/master/MCL64
I am basing the speed increase on a small BASIC test which counts the “jiffies” during a loop of code. This is the method used by the YouTube host “8-Bit Show and Tell” during his demonstration of the Super CPU Commodore 64 accelerator board:
https://www.youtube.com/watch?v=x9clez2fxxw
In cycle-accurate mode my MCL64 measures the same results as the host, but when comparing the Super CPU accelerated to 20Mhz and the MCL64 in its accelerated mode, the MCL64 is roughly 2X faster than the Super CPU (in raw accelerated mode). The Super CPU has an additional “optimized” BASIC acceleration mode which further speeds up the hardware; however if the MCL64 implemented this optimization it would most likely again be much faster than the Super CPU.
This is the YouTube demonstration of the Super CPU running in its 20Mhz acceleration mode:
This is the MCL64 running in its accelerated mode which is more than 2X faster than the Super CPU:
Small update on 12/12/2021: I created a stripped-down version of the MCL64 code which eliminates all of the 6502’s extraneous reads and writes and tried the BASIC test code once again. This time the test took around 7 jiffies! (The first pass which yielded 525 was using this optimized code without acceleration enabled)
Here are a few C64 cartridge images which I loaded into the MCL64:
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